Issues

Search results

[BUG] False warning for missing sensitivity list when using multiple parameters for edge detection and if there are multiple edge detections as if-elsif

#395 In VHDL-LS/rust_hdl;

· nselvara openedon Jun 20, 2025

Completion Type Case Config

#393 In VHDL-LS/rust_hdl;

· n8tlarsen openedon Jun 6, 2025

[BUG] Record Member Assignment Falsely Triggers "Unused Signal" Warning

#392 In VHDL-LS/rust_hdl;

· larshb openedon Jun 4, 2025

[FEATURE] Emit warnings for potential Clock Domain Crossings (CDC)

#391 In VHDL-LS/rust_hdl;

· nselvara openedon May 28, 2025

[FEATURE] Sub-project: vhdl_doc

#390 In VHDL-LS/rust_hdl;

· n8tlarsen openedon May 18, 2025

[FEATURE] Nightly build pipeline and preview version of VSCode extension

#388 In VHDL-LS/rust_hdl;

· nselvara openedon May 15, 2025

[BUG] No warning reported when using a record element accessed via record's type name as type

#387 In VHDL-LS/rust_hdl;

· nselvara openedon May 12, 2025

Multiple projects that share files

#385 In VHDL-LS/rust_hdl;

· jhartika openedon May 7, 2025

Goto definition with component in architecture

#384 In VHDL-LS/rust_hdl;

· nicobld openedon May 5, 2025

[BUG] No warning reported when a function/procedure has been declared but not defined yet in protected type

#381 In VHDL-LS/rust_hdl;

· nselvara openedon May 2, 2025

[BUG] File analysis aborted and falsely flagged as missing after prior fatal error

#375 In VHDL-LS/rust_hdl;

· nselvara openedon Apr 22, 2025

File List order

#374 In VHDL-LS/rust_hdl;

· qarlosalberto openedon Apr 2, 2025