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authorJemma Issroff <[email protected]>2022-02-02 09:14:59 -0500
committerAaron Patterson <[email protected]>2022-02-02 09:20:34 -0800
commit2913a2f5cfceb6d6b411e165d9c723bd2435eacd ()
treef5f7cd1deb656219e108de980f13291778d8eb9a /misc/lldb_disasm.py
parent7b77d46671685c837adc33b39ae0210e04cd8b24 (diff)
Treat TS_ICVARC cache as separate from TS_IVC cache
Notes: Merged: https://.com/ruby/ruby/pull/5519
-rw-r--r--misc/lldb_disasm.py2
1 files changed, 2 insertions, 0 deletions
@@ -27,6 +27,7 @@ class IseqDisassembler:
TS_CDHASH = b'H'[0]
TS_IC = b'K'[0]
TS_IVC = b'A'[0]
TS_ID = b'I'[0]
TS_ISE = b'T'[0]
TS_ISEQ = b'S'[0]
@@ -48,6 +49,7 @@ class IseqDisassembler:
TS_ISE: "(iseq_inline_storage_entry *)%0#x",
TS_ID: "ID: %0#x",
TS_IVC: "(struct iseq_inline_iv_cache_entry *)%0#x",
TS_IC: "(struct iseq_inline_cache_entry *)%0#x",
TS_CDHASH: "CDHASH (VALUE)%0#x",
TS_CALLDATA: "(struct rb_call_data *)%0#x",