3 files changed, 45 insertions, 2 deletions
@@ -118,6 +118,12 @@ impl LoadStore {
 pub fn stur(rt: u8, rn: u8, imm9: i16, num_bits: u8) -> Self {
 Self { rt, rn, idx: Index::None, imm9, opc: Opc::STR, size: num_bits.into() }
 }
 }
 /// https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Loads-and-Stores?lang=en
@@ -903,7 +903,7 @@ pub fn strh_post(cb: &mut CodeBlock, rt: A64Opnd, rn: A64Opnd) {
 pub fn stur(cb: &mut CodeBlock, rt: A64Opnd, rn: A64Opnd) {
 let bytes: [u8; 4] = match (rt, rn) {
 (A64Opnd::Reg(rt), A64Opnd::Mem(rn)) => {
- assert!(rt.num_bits == rn.num_bits, "Expected registers to be the same size");
 assert!(mem_disp_fits_bits(rn.disp), "Expected displacement to be 9 bits or less");
 LoadStore::stur(rt.reg_no, rn.base_reg_no, rn.disp as i16, rt.num_bits).into()
@@ -914,6 +914,21 @@ pub fn stur(cb: &mut CodeBlock, rt: A64Opnd, rn: A64Opnd) {
 cb.write_bytes(&bytes);
 }
 /// SUB - subtract rm from rn, put the result in rd, don't update flags
 pub fn sub(cb: &mut CodeBlock, rd: A64Opnd, rn: A64Opnd, rm: A64Opnd) {
 let bytes: [u8; 4] = match (rd, rn, rm) {
@@ -821,7 +821,11 @@ impl Assembler
 // the Arm64 assembler works, the register that is going to
 // be stored is first and the address is second. However in
 // our IR we have the address first and the register second.
- stur(cb, src.into(), dest.into());
 },
 Insn::Load { opnd, out } |
 Insn::LoadInto { opnd, dest: out } => {
@@ -1379,6 +1383,24 @@ mod tests {
 }
 #[test]
 fn test_emit_xor() {
 let (mut asm, mut cb) = setup_asm();