mod bitmask_imm;

mod condition;

mod sf;

mod shifted_imm;

mod sys_reg;

pub use bitmask_imm::BitmaskImmediate;

pub use condition::Condition;

pub use sf::Sf;

pub use shifted_imm::ShiftedImmediate;

pub use sys_reg::SystemRegister;

/// The struct that represents an A64 conditional branch instruction that can be

/// encoded.

cond: u8,

/// The instruction offset from this instruction to branch to.

}

impl BranchCond {

/// B.cond

/// https://developer.arm.com/documentation/ddi0596/2020-12/Base-Instructions/B-cond--Branch-conditionally-

}

}

0

| (1 << 30)

| (FAMILY << 26)

| (inst.cond as u32)

}

}

#[test]

fn test_b_eq() {

assert_eq!(0x54000400, result);

}

#[test]

fn test_b_vs() {

assert_eq!(0x54000406, result);

}

#[test]

fn test_b_eq_max() {

assert_eq!(0x547fffe0, result);

}

#[test]

fn test_b_eq_min() {

assert_eq!(0x54800000, result);

}

}

/// The operation to perform for this instruction.

enum Op {

/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

///

pub struct Call {

/// The operation to perform for this instruction.

op: Op

impl Call {

/// B

/// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/B--Branch-

}

/// BL

/// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/BL--Branch-with-Link-?lang=en

}

}

0

| ((inst.op as u32) << 31)

| (FAMILY << 26)

}

}

#[test]

fn test_bl() {

assert_eq!(0x94000000, result);

}

#[test]

fn test_bl_positive() {

assert_eq!(0x94000100, result);

}

#[test]

fn test_bl_negative() {

assert_eq!(0x97ffff00, result);

}

#[test]

fn test_b() {

assert_eq!(0x14000000, result);

}

#[test]

fn test_b_positive() {

assert_eq!(0x15ffffff, result);

}

#[test]

fn test_b_negative() {

assert_eq!(0x16000000, result);

}

}

/// The size of the operands being operated on.

enum Opc {

rt: u8,

/// The PC-relative number of instructions to load the value from.

/// The size of the operands being operated on.

opc: Opc

impl LoadLiteral {

/// LDR (load literal)

/// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDR--literal---Load-Register--literal--?lang=en

}

}

| ((inst.opc as u32) << 30)

| (1 << 28)

| (FAMILY << 25)

| (inst.rt as u32)

}

}

#[test]

fn test_ldr_positive() {

let result: u32 = inst.into();

assert_eq!(0x580000a0, result);

}

#[test]

fn test_ldr_negative() {

let result: u32 = inst.into();

assert_eq!(0x58ffff60, result);

}

}

/// B - branch without link (offset is number of instructions to jump)

cb.write_bytes(&bytes);

}

/// value into a register first, then use the b.cond instruction to skip past a

/// direct jump.

pub const fn bcond_offset_fits_bits(offset: i64) -> bool {

}

/// B.cond - branch to target if condition is true

cb.write_bytes(&bytes);

}

/// BL - branch with link (offset is number of instructions to jump)

cb.write_bytes(&bytes);

}

}

/// LDR - load a PC-relative memory address into a register

let bytes: [u8; 4] = match rt {

A64Opnd::Reg(rt) => {

LoadLiteral::ldr_literal(rt.reg_no, rn, rt.num_bits).into()

#[test]

fn test_bcond() {

}

#[test]

fn test_b() {

}

#[test]

#[should_panic]

fn test_b_too_big() {

// There are 26 bits available

}

#[test]

#[should_panic]

fn test_b_too_small() {

// There are 26 bits available

}

#[test]

fn test_bl() {

}

#[test]

#[should_panic]

fn test_bl_too_big() {

// There are 26 bits available

}

#[test]

#[should_panic]

fn test_bl_too_small() {

// There are 26 bits available

}

#[test]

#[test]

fn test_ldr_literal() {

}

#[test]

Target::CodePtr(dst_ptr) => {

let dst_addr = dst_ptr.into_i64();

let src_addr = cb.get_write_ptr().into_i64();

// If the jump offset fits into the conditional jump as

// an immediate value and it's properly aligned, then we

// Here we're going to return 1 because we've only

// written out 1 instruction.

// Otherwise, we need to load the address into a

// register and use the branch register instruction.

let dst_addr = dst_ptr.into_u64();

// We're going to write out the inverse condition so

// that if it doesn't match it will skip over the

// instructions used for branching.

emit_load_value(cb, Assembler::SCRATCH0, dst_addr);

br(cb, Assembler::SCRATCH0);

// offset. We're going to assume we can fit into a single

// b.cond instruction. It will panic otherwise.

cb.label_ref(label_idx, 4, |cb, src_addr, dst_addr| {

});

},

Target::FunPtr(_) => unreachable!()

// references to GC'd Value operands. If the value

// being loaded is a heap object, we'll report that

// back out to the gc_offsets list.

cb.write_bytes(&value.as_u64().to_le_bytes());

let ptr_offset: u32 = (cb.get_write_pos() as u32) - (SIZEOF_VALUE as u32);

// The offset to the call target in bytes

let src_addr = cb.get_write_ptr().into_i64();

let dst_addr = target.unwrap_fun_ptr() as i64;

// Use BL if the offset is short enough to encode as an immediate.

// Otherwise, use BLR with a register.

} else {

emit_load_value(cb, Self::SCRATCH0, dst_addr as u64);

blr(cb, Self::SCRATCH0);

let src_addr = cb.get_write_ptr().into_i64();

let dst_addr = dst_ptr.into_i64();

// If the offset is short enough, then we'll use the

// branch instruction. Otherwise, we'll move the

// destination into a register and use the branch

// register instruction.

for _ in num_insns..4 {

nop(cb);

}

// to assume we can fit into a single b instruction.

// It will panic otherwise.

cb.label_ref(*label_idx, 4, |cb, src_addr, dst_addr| {

});

},

_ => unreachable!()