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  1. lowRISC/opentitanlowRISC/opentitanPublic

    OpenTitan: Open source silicon root of trust

    SystemVerilog 2.9k 859

  2. lowRISC/ibexlowRISC/ibexPublic

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog 1.6k 618

  3. pulp-platform/axipulp-platform/axiPublic

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

    SystemVerilog 1.3k 299

  4. pulp-platform/heropulp-platform/heroPublic

    Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software …

    SystemVerilog 105 26

  5. memora-rsmemora-rsPublic

    Memora: Build Artifact Cache for Git Repositories

    Rust 8 3