verilog-project

Here are 3 public repositories matching this topic...

Arjun-Narula / Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

traffic verilog vivado verilog-hdl traffic-light traffic-sign-recognition vivado-hls verilog-programs verilog-simulator verilog-project verilog-code vivado-simulator

UpdatedJul 18, 2020
JavaScript

omid-reza / ComputerArchitectureFinalProject

Star

computer architecture course final project

javascript python php vuejs simulator vue verilog verilog-project

UpdatedDec 6, 2021
JavaScript

Karan-nevage / RISC-V-Single-Cycle-Core-Verilog-

Star

This project involves designing a single-core RISC-V CPU using Verilog. The design includes an Arithmetic Logic Unit (ALU) with flags, an assembly to machine code converter, a control unit, a microarchitecture and memory initialization to ensure proper functioning of the CPU.

verilog alu vlsi risc-v control-unit verilog-project cpu-design

UpdatedOct 11, 2024
JavaScript

Improve this page

Add a description, image, and links to the verilog-project topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the verilog-project topic, visit your repo's landing page and select "manage topics."

Learn more