AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
- Updated
Jun 12, 2025 - SystemVerilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
VeeR EH1 core
Project F brings FPGAs to life with exciting open-source designs you can build on.
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
VeeR EL2 Core
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.
Методические материалы по разработке процессора архитектуры RISC-V
Collection of IP and information on how to develop for openFPGA and Analogue Pocket
AMD OpenNIC Shell includes the HDL source files
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。
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