Here are 21 public repositories matching this topic...
- UpdatedJan 27, 2023
- Python
Support files for participating in a Fomu workshop
- UpdatedMar 17, 2024
- Verilog
FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
- UpdatedMar 16, 2023
- Python
AXI support for Migen/MiSoC
- UpdatedJun 5, 2025
- Python
Open source Logic Analyzer based on LiteX SoC
Template project for LiteX-based SoCs
- UpdatedJun 18, 2025
- Python
gateware for the main fpga, including a hispi decoder and image processing
- UpdatedSep 27, 2018
- Verilog
USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface
- UpdatedOct 24, 2017
- Verilog
Describing RTL circuit in Ruby
Scripts and gateware for the TinyFPGA bx
- UpdatedMar 18, 2020
- AGS Script
Gateware and software for Fastino (32 channel 2.5 MS/s 16 bit DAC for the Sinara ecosystem)
- UpdatedMar 2, 2023
- Python
WARC Open Fusesoc Cores Repository
CPLD gateware for the Sinara Urukul module
- UpdatedNov 18, 2021
- Python
- UpdatedApr 11, 2020
- Python
A unit-test framework for testing Migen modules directely on hardware.
- UpdatedJan 23, 2020
- Python
Hardware Motion and Motor Control Library
- UpdatedJul 22, 2023
- Python
A Python toolbox for building complex digital hardware [fork for adding nexsys3 support]
- UpdatedMay 31, 2017
- Python
- UpdatedOct 21, 2018
- Python
CPLD gateware for the Sinara Mirny module.
- UpdatedAug 20, 2024
- Python
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