verilog-hdl

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

A sample FPGA project on KV260

Examples for Gowin Tang Nano 4k FPGA-board.

c compiler beluga with riscv32 backend

16 Bit Scientific Calculator Using Xilinx ISE 14.7 on Xilinx ISE, EDA Playground and Simple 4 bit calculator on Spartan 6 Board

a lightweight Verilog-vpi Wrapper for Stimuli Generation

Neural Network implemented in Verilog used for distinguishing if the wave that bounced back into the sonar bounced off a mine or a rock.

HDL implementation of a CIC interpolation filter using verilog on nexys 4 artix 7

A generic verification interface to Verilog simulators using TCP sockets

This is a basic project of Arithmetic Logic Unit that takes two input of 8 Bits each and undergoes 8 different operations and generates an output of 16 Bits

This project is an implementation of cache memory with load and store instructions in Verilog.

Developing a MIPS-like microprocessor with cache

This is a university project. It is an implementation ant testing of MIPS processor in verilog.

FPGA design and implementation of multi-cycle 32-bits pipelined MIPS processor

Shaped by Kiel c51

Code Repository of Assignments done as part of Computer Architecture Lab course at IIT Kharagpur

A python program to generate a Pseudo Random Noise sequence called WSLCE

A 32 bit Booth Encoded Wallace Tree Multiplier in Verilog HDL.